Tiempo Secure becomes a Strategic Member of RISC V International.

Grenoble, France – October 11, 2022 – Through becoming a RISC-V Strategic Member, International Tiempo Secure is expanding its offerings with a new RISC V processor-based core TESIC Secure Element that implements the instruction set architecture specification RISC-V “RV32IMCB.”

 This evolution will provide significant advantages for the Tiempo Secure product and maintain the existing service with a proprietary processor; this new processor offers a cutting-edge, industry-standard 32-bit option.

Tiempo Secure adopts a standard architecture in this step, simplifying development and integration for customers while benefiting from the large pool of RISC V experts. Adopting the RISCV architecture allows integrators and software developers of Tiempo Secure TESIC products to work with the standard tools for development, thereby integrating into the company’s TESIC products more quickly and more straightforwardly.

Tiempo Secure is an established security specialist. Therefore their TESIC Secure Element IP solutions are certified. Tiempo Secure TESIC Secure element IP is integrated into the System on Chips that have been certified to Common Criteria EAL 5+ certification.

 Furthermore, Tiempo Secure commits to offering its integrators the highest level of support, ensuring they get security certification.

RISCV International is the worldwide non-profit headquarters for an open-standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder communities. Hardware implementations are compatible with the RISCV instruction set, which makes it simple for integrators to create software and transfer it to different hardware types.

Since RISC-V is widely used, various tools for software are available, and the community of developers is large.

Serge Maginot, the Tiempo Secure CEO, commented: “Joining RISC-V International represents an important milestone in the time of Tiempo Secure. We’ll not only be able to continue on providing specific items to our clients, but we’re making it easier for them to incorporate these products in their Systems-on-Chips as well as software.”

Calista Redmond, CEO of RISC V International, states: “We are glad to be able to see Tiempo Secure join RISCV International. Their experience with Secure Element IP development, and even more broadly, their security knowledge will make them an important stakeholder for our organization as well as our its members.”

About Tiempo Secure

Tiempo Secure is an independent SME with its headquarters in Grenoble, France, founded in 2007 with clients from Europe, North America, and Asia. They specialize in developing IP (IP) using microelectronics and embedded software to secure connected objects.

The company provides a broad assortment of Secure Elements (TESIC family) that are ready for integration in “System-on-Chip” (SoC) components and provide the highest level of safety (Common Criteria EAL5+-certified) of features that are connected that allow authentication on networks that have integrated SIM (iSIM/ICC) (iSIM/ICC), payment (EMVCo) and personal or government identity web authenticator (FIDO 2) intelligent vehicle access, communication using autonomous vehicles (V2X HSM).

For more information: www.tiempo-secure.com.

Contact: Tiempo Secure, Email: sales@tiempo-secure.com

About RISC-V International

The RISC-V International non-profit organization is the house of the open standards RISC-V Instruction Set Architecture (ISA), related specifications, and the stakeholder community. More than 3100 RISC-V members from 70 countries participate and work in developing RISC-V open specifications to convene and oversee the related industry, technical domains, and special interest groups.

The RISC-V technology combines a modular approach with a downloadable royalty-free licensing model, which means everyone can profit from the IP that the RISC-V creates. It allows the community to share investment in technology and help shape the future, develop more quickly, enjoy the most creative design freedom, and dramatically reduce the costs of innovations.

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